This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-284709, filed Sep. 20, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device using a ferroelectric film and, more particularly, to a highly integrated semiconductor memory device.
2. Description of the Related Art
A ferroelectric memory is advantageous because it is nonvolatile like a flash memory and is capable of not only a high-speed access and write like a DRAM but also low-voltage/low-power operation. For the cell structure of a ferroelectric memory, a 1-transistor/1-capacitor memory cell like a DRAM cell has been widely developed.
A ferroelectric memory cell stores the xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d state depending on whether the polarization is directed upward or downward, as shown in FIG. 27. As shown in FIG. 27, a cell transistor 100, which has a gate connected to a word line WL and a source connected to a bit line BL, is connected to a node C, i.e., an electrode of a capacitor 101 with other electrode connected to a plate line PL. The polarization amount of the ferroelectric capacitor depends on the time of voltage application to the ferroelectric capacitor. When the time is prolonged, the polarization amount becomes close to the saturated polarization amount. For this reason, even in a device, when the write time is prolonged, a sufficient polarization amount can be obtained, and the data holding characteristic improves.
In a conventional general 1-transistor/1-capacitor memory cell, to increase the reliability of cell data holding, the voltage across the ferroelectric capacitor is held after the data write to obtain sufficient polarization. That is, after the active state is ended, the word line is set in the unselected state to confine the bit line potential in the node C shown in FIG. 27. In this state, a write potential is applied to the ferroelectric capacitor by the potential difference between the node C and the plate line PL, thereby sufficiently writing the data.
A ferroelectric memory (to be referred to as a TC parallel unit series connection type ferroelectric memory hereinafter) has received a great deal of attention because of its high operation speed and high degree of integration, in which a unit cell is formed by connecting the two terminals of a capacitor (C) between the source and the drain of a cell transistor (T) and connecting a plurality of unit cells in series. This ferroelectric memory is described in xe2x80x9cA Sub-40 ns Random-Access Chain FRAM Architecture with a 7 ns Cell-Plate-Line Drive,xe2x80x9d, ISSCC Tech. Dig. Papers, pp. 102-103, Feb. 1999.
In this structure, a cell transistor 102 formed from an n-channel transistor and a capacitor 103 are connected in parallel to form one memory cell 104, as shown in FIG. 28. A plurality of memory cells 104 are connected in series to form a memory cell block 105. Pairs of memory cell blocks 105 are laid out in multiple stages (one stage in FIG. 28), and each of the paired memory cell blocks 105 is arranged between a corresponding one of bit lines BL and BLB and a corresponding one of plate lines PL1 and PL2. Block selection transistors 106 with gates connected to block selection lines BS0 and BS1 are connected between the bit lines BL and BLB and the memory cells 104 in the respective memory cell blocks 105.
In the standby mode, all the word lines WL are set at xe2x80x9cHxe2x80x9d level, and the two electrodes of each capacitor are short-circuited. In the active mode, a selected word line WL changes from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level, and the block selection line BS changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level. After that, the plate line PL changes to Vdd level to apply a Vdd potential to a selected capacitor. Data is read from the memory cell to the bit line BL. An unselected capacitor is held in the short-circuit state. In this way, a random access is done.
FIG. 29 is a view showing the arrangement of a control circuit for controlling a read/write from/to a memory cell. This control circuit has multiple stages of first to third and fifth to ninth delay circuits 107 to 114 connected in series, NAND circuit 115, inverter circuit 116, and NOR circuit 117. The control circuit receives a chip enable signal CE1 and generates and outputs two chip enable delay signals CED1 and CED2, address pass signal BADPAS, row address latch signal BRAT, row address enable signal RAE, block selection enable signal BSEBL, sense amplifier enable signal SAEBL, and plate line enable signal PLEBL.
The first chip enable delay signal CED1 controls signals for driving a block selection line drive circuit (not shown), plate line PL, and sense amplifier (not shown) which control the memory cell array. The second chip enable delay signal CED2 controls an address buffer (not shown) to control the timing of the word line WL and also controls the row address latch signal BRAT and row address enable signal RAE for driving the address buffer. The address pass signal BADPAS controls the timing to send an external address signal to the address buffer. The block selection enable signal BSEBL controls the block selection line drive circuit. The sense amplifier enable signal SAEBL controls the sense amplifier. The plate line enable signal PLEBL controls the plate line PL.
The chip enable signal CE1 is the output signal from an input buffer (not shown) for receiving an external signal CEB, and is set at xe2x80x9cHxe2x80x9d level in the active mode and at xe2x80x9cLxe2x80x9d level at the standby mode.
FIG. 30 is a timing chart showing input and output signals and signals at the respective nodes in the circuits, shown in FIGS. 28 and 29, of the conventional TC parallel unit series connection type ferroelectric memory in the read mode. Referring to FIG. 30, the signals are synchronized at timings indicated by dotted lines.
The external chip enable signal CEB changes from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level only during a predetermined period.
When the external chip enable signal CEB has changed from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level, the chip enable signal CE1 output from a chip enable buffer changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level. When the external chip enable signal CEB has changed from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, the chip enable signal CE1 changes from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level.
After the elapse of time (1)+time (2) from the timing when the chip enable signal CE1 changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, the first chip enable delay signal CED1 changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level. After the elapse of times (1) and (2)+time (3) from the timing when the chip enable signal CE1 changes from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level, the first chip enable delay signal CED1 changes from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level. The total time (1)+(2)+(3) is about 20 nsec.
After the elapse of time (1) from the timing when the chip enable signal CE1 changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, the second chip enable delay signal CED2 changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level. When the first chip enable delay signal CED1 has changed to xe2x80x9cLxe2x80x9d level, the second chip enable delay signal CED2 changes from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level.
When the chip enable signal CE1 changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, the address pass signal BADPAS simultaneously changes from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level.
After the elapse of time (5) from the change to xe2x80x9cLxe2x80x9d level, the address pass signal BADPAS changes from xe2x80x9cxe2x80x9d level to xe2x80x9cHxe2x80x9d level again.
When the second chip enable delay signal CED2 has changed from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, the row address latch signal BRAT changes from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level. After the elapse of time (6) from the timing when the change of second chip enable delay signal CED2 has changed from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level, the row address latch signal BRAT changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level.
After the elapse of time (7) from the timing when the second chip enable delay signal CED2 has changed from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, the row address enable signal RAE changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level. When the second chip enable delay signal CED2 has changed from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level, the row address enable signal RAE changes from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level.
When the row address enable signal RAE has changed from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, the word line WL1 is selected by a decoder (not shown), and its potential changes from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level. When the row address enable signal RAE has changed from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level, the word line WL1 is unselected, and its potential changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level.
When the first chip enable delay signal CED1 has changed from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, the potential of the block selection line BS0 changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level. When the first chip enable delay signal CED1 has changed from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level, the block selection line BS0 changes from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level. When the block selection line BS0 is at xe2x80x9cHxe2x80x9d level, the bit line and memory cell are connected.
When the first chip enable delay signal CED1 has changed from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, the potential of the plate line PL2 changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level. When the chip enable signal CE1 changes from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level, the potential of the plate line PL2 simultaneously changes from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level.
After the elapse of time (8)+time (9) from the timing when the first chip enable delay signal CED1 has changed from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, a sense amplifier control signal SA changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level. After the elapse of time (8) from the timing when the first chip enable delay signal CED1 has changed from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level, the sense amplifier control signal SA changes from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level.
When the potential of the plate line PL2 changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, charges are transferred from the selected memory cell to the bit line BLB, and the bit line BLB is set at a potential corresponding to the data in the memory cell. When the sense amplifier control signal SA changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, the potential of the bit line BLB is amplified to xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level in accordance with the data in the memory cell by the operation of the sense amplifier. If at xe2x80x9cHxe2x80x9d level, the potential of the bit line BLB changes to xe2x80x9cLxe2x80x9d level when the sense amplifier control signal SA has changed from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level.
After the block selection line BS0 has changed from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, the potential of a node A is connected to the bit line BLB. When the plate line PL2 changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, the bit line BLB changes to a bit line potential corresponding to the data in the memory cell, and the node A also changes to the bit line potential. When the sense amplifier control signal SA changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, the node A changes to xe2x80x9cHxe2x80x9d level or xe2x80x9cLxe2x80x9d level, like the bit line. When the block selection line BS0 changes from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level and then the potential of the word line WL1 changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, the cell transistor 102 is turned on, and the nodes A and B are short-circuited. At this time, since all the cell transistors of the memory cells are ON, the potentials of the nodes A and B equal the level of the plate line PL2.
The conventional semiconductor memory device with the above structure has the following problems.
In the cell structure of the conventional TC parallel unit series connection type ferroelectric memory, when a word line is set in the unselected state simultaneously with the end of the active state, as in a conventional 1-transistor/1-capacitor memory cell, the two terminals of the ferroelectric capacitor are short-circuited. For this reason, the write voltage cannot be continuously applied.
That is, in the cell structure of the conventional TC parallel unit series connection type ferroelectric memory, it is difficult to ensure a long rewrite time and write time, which are available in a 1-transistor/1-capacitor cell, and obtain the same write characteristic as in the 1-transistor/1-capacitor cell.
Especially, when a high-speed write with a write time of 10 to 40 nsec is executed, and the write voltage varies within the range of 10 mV and 20 mV, the data holding characteristic changes depending on the characteristics of a ferroelectric thin film.
Particularly, in rewrite operation after a read, the potential of the selected word line WL for which the write is instructed quickly changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level after the block selection line BS changes from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level.
As described above, in the conventional semiconductor memory device, since the block selection line BS and word line WL are almost simultaneously set in the unselected state, a sufficient time for the rewrite cannot be ensured.
As indicated on the signal waveform of the potential of the word line WL1 shown in FIG. 30, a xe2x80x9c0xe2x80x9d rewrite time and xe2x80x9c1xe2x80x9d write time are set. Especially, the xe2x80x9c1xe2x80x9d rewrite time is set to about 20 ns in accordance with the delay times (1), (2), and (3) by the delay circuits 1 to 3.
For this reason, the cell is not sufficiently polarized, and the bit line potential in the read becomes low. Hence, the data holding characteristic degrades, and the reliability considerably decreases.
According to an aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of memory cells coupled in series to form a memory cell block, which data is read out and data is written in, each memory cell having a cell transistor for selecting the memory cell and a ferroelectric capacitor coupled between a source and a drain of the cell transistor; a word line coupled to a gate of the cell transistor; a memory cell block selection transistor coupled to one terminal of the memory cell block of the plurality of memory cells;
a bit line coupled to the memory cell block selection transistor; a plate line coupled to the other terminal of the memory cell block of the plurality of memory cells; and a word line control circuit for controlling the word line to keep the cell transistor selected even after the memory cell block selection transistor is turned off.
According to another aspect of the present invention, there is further provided a semiconductor memory device comprising: a plurality of memory cells coupled in series to form a memory cell block, which data is read out and data is written in, each memory cell having a cell transistor for selecting the memory cell and a ferroelectric capacitor coupled between a source and a drain of the cell transistor; a word line coupled to a gate of the cell transistor; a memory cell block selection transistor coupled to one terminal of the memory cell block of the plurality of memory cells; a bit line coupled to the memory cell block selection transistor; a plate line selection transistor coupled to the other terminal of the memory cell block of the plurality of memory cells; a plate line connected to the plate line selection transistor; and a word line control circuit for controlling the word line to keep the cell transistor selected even after the memory cell block selection transistor and the plate line selection transistor are turned off.